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Advanced HDL synthesis and SOC prototyping: RTL design using Verilog
by Taraate, VaibbhavPublished by: Singapore : Springer , 2019
- Sublocation
- EGC
- Call Number
- 621.3815 T17a 2019
- Physical Desc.
- xxi, 307 p.
- ISBN
- 978-981-10-8776-9
- Copies
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